Renesas Design Vietnam deploys AI-driven verification for car chips

Renesas Electronics in Vietnam is utilizing one of the world’s latest AI-driven chip verification and debug tools to power up the development of its R-Car automotive designs.

Ho Chi Minh City-based Renesas Design Vietnam of Japanese firm Renesas Electronics is using the Verisium AI-driven verification platform from American software company Cadence Design Systems to provide root cause analysis of bugs in chip design, improving debugging productivity.

As for Renesas Electronics, the brand Renesas is a contraction of Renaissance Semiconductor for Advanced Solutions; and its R-Car platform addresses a wide range of automotive applications like automated driving or ADAS.

In September 2022, Renesas signed a strategic partnership with Vietnamese electric vehicle maker VinFast to expand their agreement in automotive technology development of EVs and delivery of system components.

San Jose, California-based Cadence (Nasdaq: CDNS) said its Verisium platform provides a holistic debugging environment from intellectual property to system-on-chip (SoC) designs, and from single-run to multi-run, enabling fast and comprehensive interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies.

The platform and apps, including Versium AutoTriage, Verisium SemanticDiff, Verisium WaveMiner, Verisium PinDown, Verisium Debug, and Verisium Manager, are integrated with the Cadence joint enterprise data and AI (JedAI) platform to enable AI-driven root cause analysis of bugs.

“Quality and efficiency are paramount to ensure our R-Car designs are completed on schedule,” Renesas Design Vietnam president Noriaki Sakamoto said in a Cadence release from San Jose Friday.

“Cadence’s Verisium Debug allows our engineers to debug from intellectual property to SoC-level designs. The new waveform format is well-designed for modern verification needs and helps to improve simulation probing performance by two times. By using the Verisium AI-Driven apps, we could improve the entire debug productivity by up to six times and our design teams have shortened our overall verification cycle.”

Paul Cunningham, senior vice president and general manager of the system & verification group of Cadence, said: “By bringing together all the inputs and outputs of our verification full flow under the Cadence JedAI platform, we are able to create a new class of Verisium AI-driven apps that dramatically improves verification productivity and efficiency for our customers.”